Hi,
I am using a Pico 2 to prototype a pulse train generator. This involves 1 PIO SM to wait for an external trigger pulse which then triggers another PIO SM write to external AD9708 DAC at 30MHz to produce an envelope. The DAC data is pre-generated and a DMA request is setup for it. After the DMA is done the code then re-arms the DMA (in the real thing it might switch to a different pulse or abort on error etc). I have an additional SM which is reading out another block of data to control external circuitry.
I managed to get this working by cascading IRQs, ie my trigger.pio is:And dac.pio:And ctrl.pio:Initially I tried having the 2 SMs block on the same IRQ but they seem to race and the SMs do not both fire in that case. The PIO docs do say "WAIT 1 IRQ x should not be used with IRQ flags presented to the interrupt controller, to avoid a race condition with a system interrupt handler" however these are not connected to an IRQ handler.
Is this expected to work? The cascade seems fine for now but by my reading of the docs it should not be necessary.
I have also tried using "wait 0 irq DAC_TRIGGER_IRQ" and then "irq clear DAC_TRIGGER_IRQ" (and NOP in the ctrl SM) but that does not work at all.
The code is at: https://hg.sr.ht/~darius/modulator/browse?rev=tip
The "WITH_TRIGGER" define turns on using trigger.pio, otherwise the code uses force_irq to manually trigger each PWM wrap (easier debugging).
Thanks
I am using a Pico 2 to prototype a pulse train generator. This involves 1 PIO SM to wait for an external trigger pulse which then triggers another PIO SM write to external AD9708 DAC at 30MHz to produce an envelope. The DAC data is pre-generated and a DMA request is setup for it. After the DMA is done the code then re-arms the DMA (in the real thing it might switch to a different pulse or abort on error etc). I have an additional SM which is reading out another block of data to control external circuitry.
I managed to get this working by cascading IRQs, ie my trigger.pio is:
Code:
.program trigger.define DAC_TRIGGER_IRQ 0.define CTRL_TRIGGER_IRQ 1; Use 1 side set pin for debugging.side_set 1.wrap_target; Wait for trigger to be low wait 0 pin 0 side 0; Wait for rising edge wait 1 pin 0 side 0; Signal DAC SM (which will trigger the control one) irq nowait DAC_TRIGGER_IRQ side 1.wrapCode:
.program dac.define DAC_IRQ 0.define DAC_TRIGGER_IRQ 0.define CTRL_TRIGGER_IRQ 1; Need 1 side set pin, the clock.side_set 1; Clock in a 0 byte mov pins, null side 0 nop side 1; Wait for start trigger and clear IRQ wait 1 irq DAC_TRIGGER_IRQ side 0; Trigger the control SM irq nowait CTRL_TRIGGER_IRQ side 0; Clock DAC and write data from the FIFO; DAC clocks data in on the rising clock edge.wrap_target out pins 8 side 0 nop side 1 out pins 8 side 0 nop side 1 out pins 8 side 0 nop side 1 out pins 8 side 0 nop side 1.wrapCode:
.program ctrl.define DAC_TRIGGER_IRQ 0.define CTRL_TRIGGER_IRQ 1; Assert all 0s mov pins, null; Wait for start trigger and clear IRQ wait 1 irq CTRL_TRIGGER_IRQ.wrap_target out pins 8 nop out pins 8 nop out pins 8 nop out pins 8 nop.wrapIs this expected to work? The cascade seems fine for now but by my reading of the docs it should not be necessary.
I have also tried using "wait 0 irq DAC_TRIGGER_IRQ" and then "irq clear DAC_TRIGGER_IRQ" (and NOP in the ctrl SM) but that does not work at all.
The code is at: https://hg.sr.ht/~darius/modulator/browse?rev=tip
The "WITH_TRIGGER" define turns on using trigger.pio, otherwise the code uses force_irq to manually trigger each PWM wrap (easier debugging).
Thanks
Statistics: Posted by Darius121 — Tue Feb 25, 2025 6:32 am — Replies 2 — Views 60